The present invention relates to non-volatile memory transistors employing hot carrier injection, arrays of such memory transistors, electronic devices employing such memory transistors and methods related to such memory transistors.
Various types of memory devices are used in electronic systems. Some types of memory device, such as DRAM (dynamic random access memory) provide large amounts of readable and writable data storage with modest power budget and in favorably small form factor, but are not as fast as other types of memory devices and provide volatile data storage capability.
Volatile data storage means that the memory must be continuously powered in order to retain data, and the stored data are lost when the power is interrupted. Nonvolatile memories are capable of retaining data without requiring electrical power.
Other types of memory can provide read-only or read-write capabilities and non-volatile data storage, but are much slower in operation. These include CD-ROM devices, CD-WORM devices, magnetic data storage devices (hard discs, floppy discs, tapes and the like), magneto-optical devices and the like.
Still other types of memory provide very high speed operation but also demand high power budgets. Static RAM or SRAM is an example of such memory devices.
In most computer systems, different memory types are blended to gain the benefits that each technology can offer. For example, read-only memories or ROM, EEPROM and the like are typically used to store limited amounts of infrequently-accessed data such as a basic input-output system. These memories are employed to store data that, in response to a power ON situation, configure a processor to be able to load larger amounts of software such as an operating system from a high capacity non-volatile memory device such as a hard drive. The operating system and application software are typically read from the high capacity memory and corresponding images are stored in DRAM.
As the processor executes instructions, some types of data may be repeatedly fetched. As a result, some SRAM or other high speed memory is typically provided as xe2x80x9ccachexe2x80x9d memory in conjunction with the processor and may be included on the processor chip or very near it.
Several different kinds of memory device are involved in most modern computing devices, and in many types of appliances that include automated and/or programmable features (home entertainment devices, telecommunications devices, automotive control systems etc.). As system and software complexity increase, need for memory in creases. Desire for portability, computation power and/or practicality result in increased pressure to reduce both power consumption and circuit area per bit. Modern computing devices employ relatively large amounts of DRAMs for temporary data storage.
However, because DRAMs are volatile memories, they require xe2x80x9crefreshxe2x80x9d operations. In a refresh operation, data are read out of each memory cell, amplified and written back into the DRAM. As a first result, the DRAM circuit is usually not available for other kinds of memory operations during the refresh operation. Additionally, refresh operations are carried out periodically, resulting in periods during which data cannot be readily extracted from or written to DRAMs. As a second result, some amount of electrical power is always needed to store data in DRAM devices.
As a third result, boot operations for computers such as personal computers involve a period during which the computer cannot be used following power ON operation. During this period, operating system instructions and data, and application instructions and data, are read from relatively slow, non-volatile memory, such as a conventional disc drive, are decoded by the processing unit and the resultant instructions and data are loaded into modules incorporating relatively rapidly-accessible, but volatile, memory such as DRAM. Other consequences flow from the properties of the memory systems included in various electronic devices and the increasingly complex software employed with them, however, these examples serve to illustrate ongoing needs.
Flash memory devices have been developed to address some of these concerns. Flash memory devices typically employ a floating gate and operate by creating xe2x80x9chotxe2x80x9d charge carriers that are then injected through an insulator into the floating gate. Alternatively, the xe2x80x9chotxe2x80x9d charge carriers may be injected into and trapped within a suitable dielectric medium. These kinds of devices typically are combined with an MOS structure to enable the data to be read out of the device.
Problems that are encountered with such devices include relatively low injection efficiency, latch-up phenomena and/or silicon-on-insulator (SOI) floating-body effects. As device geometries are scaled to smaller and smaller sizes, need increases for reducing channel or ON resistance, reducing parasitic capacitance and reducing short-channel effects in such devices.
Needed are methods and apparatus relating to non-volatile memory providing high areal data storage capacity, reprogrammability, low power consumption and relatively high data access speed, coupled with reduced ON resistance, improved charge carrier injection efficiency and reduced short-channel effects.
In one aspect, the invention includes a method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.
In one aspect, the invention includes a memory transistor structure. The memory transistor structure includes a substrate comprising semiconductive material and spaced-apart source/drain structures. At least one of the source/drain structures includes a Schottky contact to the semiconductive material. The memory transistor structure includes a memory gate disposed between the spaced-apart source/drain structures and a control gate disposed operatively over the memory gate.